Semiconductor memory device and method of controlling the same

ABSTRACT

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. Ser. No. 14/601,664 filed Jan. 21, 2015which is a continuation of U.S. Ser. No. 14/231,140, filed Mar. 31, 2014(now U.S. Pat. No. 8,959,411 issued Feb. 17, 2015), which is acontinuation of U.S. Ser. No. 13/757,935, filed Feb. 4, 2013, (now U.S.Pat. No. 8,732,544, issued May 20, 2014), which is a divisional of U.S.Ser. No. 13/465,624, filed May 7, 2012 (now U.S. Pat. No. 8,386,881issued Feb. 26, 2013), which is a continuation of U.S. Ser. No.13/090,539, filed Apr. 20, 2011 (now U.S. Pat. No. 8,196,008 issued Jun.5, 2012), which is a continuation of U.S. Ser. No. 12/404,861, filedMar. 16, 2009 (now U.S. Pat. No. 8,117,517 issued Feb. 14, 2012), whichis a continuation of PCT Application No. PCT/JP08/063344, filed Jul. 17,2008, which was published under PCT Article 21(2) in Japanese, and alsoclaims the benefit of priority from Japanese Patent Application No.2007-225996 filed Aug. 31, 2007, the entire contents of each of whichare incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amethod of controlling the same and, for example, to a memory devicewhich nonvolatilely stores information and has an error correctioncircuit, and a method of controlling the memory device.

2. Description of the Related Art

In some kinds of nonvolatile memory devices, the state of the physicalquantity that controls data storage changes along with the elapse oftime. If the elapsed time has reached a predetermined length, the datamay be lost. There are various types of memory devices having such acharacteristic feature. One of such memory devices is, e.g., anonvolatile semiconductor memory device which uses transistors having aso-called laminated gate structure as memory cells.

The laminated gate structure includes a tunnel insulating film, floatinggate electrode, inter-electrode insulating film, and control gateelectrode which are sequentially stacked on a substrate. To storeinformation in a memory cell, electrons are injected from the substrateto the floating gate electrode through the tunnel insulating film. Theelectric charges accumulated in the floating gate electrode retaininformation. The electric charges accumulated in the floating gateelectrode leak to the substrate through the tunnel insulating film asthe time elapses. For this reason, the information retained in thememory cell can be lost along with the elapse of time (an error canoccur in the information).

If the elapsed time from the information storage time is short, an errorcan rarely occur in the information. On the other hand, if a long timehas elapsed after information storage, an error may occur in theinformation at a high probability. A memory device having a plurality ofsuch memory cells sometimes includes an error correction mechanism forrestoring erroneous information to a correct state.

Generally, to correct a number of errors which are contained in dataformed from a plurality of bits due to, e.g., the elapse of time frominformation recording, a correction mechanism having a high errorcorrection capability is necessary. A correction mechanism with a higherror correction capability has a large circuit scale and requires highpower consumption and a long time for processing. Normally, to guaranteeto restore correct information even after the elapse of a long time frominformation storage, a memory device uses a correction mechanism havinga high error correction capability. The high-performance errorcorrection mechanism is applied equally regardless of the length of theelapsed time from information storage.

For this reason, even in reading information which has been stored foronly a short time, the high-performance error correction mechanism isused. Since the information to be read contains not so many errors, theuse of the high-performance error correction mechanism is wasteful. Thisleads to a waste of power in the memory device.

To increase the error correction capability, generally, the size of theerror correction target information needs to be large. For example, anerror-correcting code is generated not for 512-byte data but for, e.g.,4-kbyte data obtained by concatenating a plurality of 512-byte data.This increases the error correction capability. In this method, however,it is necessary to always read out 4-kbyte data even in reading out512-byte data. This also results in a waste of power in the memorydevice.

Prior-art reference information related to this application is

JP-A 63-275225 (KOKAI)

In the reference, a correction apparatus which has a high errorcorrection capability is disclosed.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided asemiconductor memory device comprising: a plurality of detecting codegenerators configured to generate a plurality of detecting codes todetect errors in a plurality of data items, respectively; a plurality offirst correcting code generators configured to generate a plurality offirst correcting codes to correct errors in a plurality of first datablocks, respectively, each of the first data blocks containing one ofthe data items and a corresponding detecting code; a second correctingcode generators configured to generate a second correcting code tocorrect errors in a second data block, the second data block containingthe first data blocks; and a semiconductor memory configured tononvolatilely store the second data block, the first correcting codes,and the second correcting code.

According to an aspect of the present invention, there is provided asemiconductor memory device comprising: A method of controlling asemiconductor memory device, the method comprising: generating aplurality of detecting codes to detect errors in a plurality of dataitems, respectively; generating a plurality of first correcting codes tocorrect errors in a plurality of first data block, respectively, each ofthe first data blocks containing one of the data items and acorresponding detecting code; generating a second correcting code tocorrect errors in a second data block, the second data block containingthe first data blocks; and nonvolatilely storing the second data block,the first correcting codes, and the second correcting code.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram schematically illustrating a semiconductormemory device according to an embodiment;

FIG. 2 is a block diagram illustrating the main portion of an errorcorrection circuit associated with data write;

FIG. 3 is a view illustrating a data state in a temporary storagecircuit 3 in write;

FIG. 4 is a view illustrating a state following FIG. 3;

FIG. 5 is a view illustrating a state following FIG. 4;

FIG. 6 is a block diagram illustrating the main portion of the errorcorrection circuit associated with data read;

FIG. 7 is a view illustrating an example of the operation of a seconderror correction unit;

FIG. 8 is a graph illustrating the relationship between the necessarycorrection capability and the elapsed time from write;

FIG. 9 is a view illustrating the concept of the process range of afirst error correction unit 11 and that of the second error correctionunit 13;

FIG. 10 is a graph illustrating the relationship between the error rateand the use probability of the second error correction unit; and

FIG. 11 is a graph illustrating the relationship between the error rateand averaged Chien search of the second error correction unit.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will now be described withreference to the accompanying drawing. In the following description, thesame reference numerals denote constituent elements having almost thesame functions and arrangements, and a repetitive explanation will bemade only when necessary.

The embodiments to be described below are mere examples of an apparatusor method to embody the technical scope of the present invention. Thetechnical scope of the present invention does not limit the materials,shapes, structures, and arrangements of the components to thosedescribed below. The technical scope of the present invention allowsvarious changes and modifications in the appended claims.

The functional blocks of the embodiments of the present invention can beimplemented by hardware, computer software, or a combination thereof.The blocks will be described below generally from the viewpoint of theirfunctions while clarifying that they can be implemented by both ofhardware and software. Whether to execute a function as hardware orsoftware depends on the specific embodiments or design restrictions onthe entire system. Those skilled in the art can implement the functionby various methods for each of the specific embodiments, and the presentinvention incorporates such implementation.

FIG. 1 is a block diagram schematically illustrating a semiconductormemory device according to an embodiment.

As shown in FIG. 1, a semiconductor memory device 10 includes an errorcorrection circuit 1 and a semiconductor memory 2. The error correctioncircuit 1 and the semiconductor memory 2 are formed as, e.g., onesemiconductor integrated circuit on a single semiconductor chip. Thesemiconductor memory 2 can be any memory device if it can nonvolatilelystore information, and the stored data can be changed. An example of thesemiconductor memory 2 is a NAND flash memory.

A NAND flash memory has a plurality of memory cells. Each memory cell isformed from a MOSFET (metal oxide semiconductor field effect transistor)having a so-called laminated gate structure. A MOS transistor with thelaminated gate structure includes a tunnel insulating film, floatinggate electrode, inter-electrode insulating film, control gate electrode,and source and drain diffusion layers. The threshold voltage of eachmemory cell transistor is changed in accordance with the amount ofelectric charge accumulated in the floating gate electrode, and eachmemory cell transistor stores information corresponding to the change inthe threshold voltage. The memory cell transistor can be designed tostore either 1-bit information or information of a plurality of bits. Acontrol circuit including a sense amplifier and a potential generationcircuit in the semiconductor memory 2 can write data supplied to thesemiconductor memory 2 in the memory cell transistors, or output datastored in the memory cell transistor outside the semiconductor memory 2.

The control gate electrodes of memory cell transistors belonging to thesame row are connected to a single word line. A select gate transistoris provided at each of the ends of memory cell transistors which belongto the same column and are connected in series. One select gatetransistor is connected to a bit line. Based on this rule, the memorycell transistors, select gate transistors, word lines, and bit lines areprovided. Data write and read are done for each set of a plurality ofmemory cell transistors. A storage area formed from a set of memory celltransistors corresponds to one page. A plurality of pages form a block.The NAND flash memory erases data in each block.

Data (write data) required to be written in the semiconductor memory 2is externally supplied to the semiconductor memory device 10. The errorcorrection circuit 1 adds an error-correcting code and anerror-detecting code to the write data and supplies it to thesemiconductor memory 2. The semiconductor memory 2 stores the write datawith the error-correcting code and the error-detecting code.

In response to a control signal supplied to the semiconductor memorydevice 10, the semiconductor memory 2 supplies data (read data) requiredto be read, and an error-correcting code and an error-detecting codeadded to the read data to the error correction circuit 1. The errorcorrection circuit 1 detects and corrects an error in the read data. Ifan error exists, the error correction circuit 1 corrects it, removes theerror-correcting code and the error-detecting code, and outputs the readdata to an external device.

[Arrangement of Write System Circuit]

FIG. 2 is a block diagram illustrating the main portion of the errorcorrection circuit 1 associated with data write. The error correctioncircuit 1 generates an error-correcting code for each of a plurality ofwrite data each having a predetermined size and also generates anothererror-correcting code for the set of plurality of write data. The numberof write data is decided in accordance with the error correctioncapability desired to achieve and the error-correcting codes to beemployed. An example in which the number of write data is 8 will bedescribed below.

As shown in FIG. 2, the error correction circuit 1 receives write dataitems Da1 to Da8. The first size can match, e.g., the size of write orread data of the semiconductor memory 2. More specifically, when a NANDflash memory is used as the semiconductor memory 2, the write data sizecorresponds to the size of one page, which is, e.g., 512 bytes. In thefollowing example, the first size is 512 bytes, for descriptiveconvenience.

The error correction circuit 1 has a temporary storage circuit 3. Thetemporary storage circuit 3 is formed from, e.g., a volatile storagecircuit and can be, e.g., a DRAM (dynamic random access memory). Thetemporary storage circuit 3 serves as a temporary storage area in writewhen generating an error-detecting code and an error-correcting code forwrite data to the semiconductor memory 2. In write, the temporarystorage circuit 3 receives the write data items Da1 to Da8. Thetemporary storage circuit 3 stores the write data items Da1 to Da8.

The write data items Da1 to Da8 are supplied to error-detecting codegeneration units 41 to 48 (some are not illustrated), respectively.

The error-detecting code generation units 41 to 48 generate (data of)error-detecting codes Db1 to Db8 for the write data items Da1 to Da8,respectively. The error-detecting codes Db1 to Db8 are used to detecterrors in the write data items Da1 to Da8. A code that allows theerror-detecting code generation units to easily calculate codes andreduce the power consumption while achieving the above-described objectis used as the error-detecting codes Db1 to Db8. For example, CRC(Cyclic Redundancy Checksum) 32 or CRC16 is usable as theerror-detecting code. The error-detecting codes Db1 to Db8 are suppliedto the temporary storage circuit 3.

The error-detecting codes Db1 to Db8 are also supplied to firsterror-correcting code generation units 61 to 68, respectively. The firsterror-correcting code generation units 61 to 68 also receive the writedata items Da1 to Da8, respectively.

The first error-correcting code generation units 61 to 68 generate firsterror-correcting codes using the write data items Da1 to Da8 and theerror-detecting codes Db1 to Db8. The first error-correcting codegenerated by the first error-correcting code generation unit 61 is usedto correct errors in the write data item Da1 and the error-detectingcode data Db1. Similarly, the first error-correcting codes generated bythe first error-correcting code generation units 62 to 68 are used tocorrect errors in the write data items Da2 to Da8 and theerror-detecting code data Db2 to Db8.

As the first error-correcting code, for example, a code which has arelatively low error correction capability of about 1 bit, requires nohigh power and no long time for calculation, and needs only a smallscale circuit for execution is usable. More specifically, for example, aHamming code is usable as the first error-correcting code.

The first error-correcting code generation units 61 to 68 output (dataof) first error-correcting codes Dc1 to Dc8, respectively. The firsterror-correcting codes Dc1 to Dc8 are supplied to the temporary storagecircuit 3.

The error-detecting codes Db1 to Db8 are supplied to a seconderror-correcting code generation unit 8. The second error-correctingcode generation unit 8 also receives the write data items Da1 to Da8.The second error-correcting code generation unit 8 generates a seconderror-correcting code using the write data items Da1 to Da8 and theerror-detecting codes Db1 to Db8. The second error-correcting code isused to correct errors in the write data items Da1 to Da8 and theerror-detecting codes Db1 to Db8.

As the second error-correcting code, for example, a code which enableserror correction at a higher capability than the error correction usingthe first error-correcting code and can correct errors of multiple bits,although the calculation amount is large, is usable. More specifically,for example, a BHC code, Reed-Solomon (RS) code, or LDPC (Low DensityParity Check) code is usable as the second error-correcting code. Thecircuit scale, power consumption, and calculation time of the seconderror-correcting code generation unit 8 exceed those of the firsterror-correcting code generation units 61 to 68 because of the largecalculation amount. However, the second error-correcting code generationunit 8 has a higher error correction capability than the firsterror-correcting code generation units 61 to 68.

The second error-correcting code generation unit 8 supplies (data of) asecond error-correcting code Dd to the temporary storage circuit 3. Thetemporary storage circuit 3 supplies, to the semiconductor memory 2, thewrite data items Da1 to Da8, error-detecting codes Db1 to Db8, firsterror-correcting codes Del to Dc8, and second error-correcting code Dd,which have structures to be described later.

[Operation in Data Write]

The operation of the error correction circuit 1 in data write will bedescribed next with reference to FIGS. 3 to 6. FIGS. 3 to 6schematically show data states in the temporary storage circuit 3 inwrite sequentially.

First, as shown in FIG. 3, the eight write data items Da1 to Da8 to bewritten in the semiconductor memory 2 are supplied to the errorcorrection circuit 1. The write data items Da1 to Da8 are stored in thetemporary storage circuit 3.

Next, as shown in FIG. 4, the write data items Da1 to Da8 are suppliedto the error-detecting code generation units 41 to 48, respectively. Theerror-detecting code generation units 41 to 48 generate theerror-detecting codes Db1 to Db8 for the write data items Da1 to Da8,respectively. When CRC32 is used as the error-detecting codes, each ofthe error-detecting codes Db1 to Db8 has a size of 32 bits.

The write data item Da1 and the error-detecting code Db1 concatenatedafter the write data item Da1 form first data block D1 that is a unit oferror correction. Similarly, the write data items Da2 to Dab and theerror-detecting codes Db2 to Db8 concatenated after them form first datablocks D2 to D8. The first data blocks D1 to D8 are stored in thetemporary storage circuit 3. Those skilled in the art already know thedetailed arrangement of the error-detecting code generation units 41 to48, and a description thereof will be omitted. In this embodiment, theerror-detecting code generation units 41 to 48 perform the detectingcode generation operations in parallel. The parallel operations of theerror-detecting code generation units 41 to 48 shorten the processingtime.

Next, as shown in FIG. 5, the first data blocks D1 to D8 are supplied tothe first error-correcting code generation units 61 to 68, respectively.The first error-correcting code generation unit 61 generates, using thefirst data block D1, the first error-correcting code Dc1 for correctingerrors in the first data block D1. The first error-correcting code Dc1is concatenated after the error-detecting code Db1 and before the writedata item Da2 and stored in the temporary storage circuit 3.

Similarly, the first error-correcting code generation units 62 to 68respectively generate, using the first data blocks D2 to D8, the firsterror-correcting codes Dc2 to Dc8 for correcting errors in the firstdata blocks D2 to D8. The first error-correcting code Dc2 isconcatenated after the error-detecting code Db2 and before the writedata item Da3 and stored in the temporary storage circuit 3. Similarly,the first error-correcting codes Dc3 to Dc7 are respectivelyconcatenated after the error-detecting codes Db3 to Db7 and before thewrite data items Da4 to Da8 and stored in the temporary storage circuit3. The first error-correcting code Dc8 is concatenated after theerror-detecting code Db8 and stored in the temporary storage circuit 3.

When the Hamming code is used as the first error-correcting code, eachof the first data blocks D1 to D8 has a size corresponding to write data(4096 bits)+error-detecting code (32 bits). To correct a 1-bit error inthe first data block D1 to D8, each of the first error-correcting codesDc1 to Dc8 has a size of, e.g., 13 bits. Those skilled in the artalready know the detailed arrangement of the first error-correcting codegeneration units 61 to 68, and a description thereof will be omitted. Inthis embodiment, the first error-correcting code generation units 61 to68 perform the correcting code generation operations in parallel. Theparallel operations of the first error-correcting code generation units61 to 68 shorten the processing time.

The first data blocks D1 to D8 are concatenated in order to form asecond data block. The second data block is supplied to the seconderror-correcting code generation unit 8. The second data block is a unitof data to be used by the second error-correcting code generation unitto generate the second error-correcting code. The seconderror-correcting code generation unit 8 generates, using the second datablock, the second error-correcting code Dd for correcting errors in thesecond data block. The second error-correcting code Dd is concatenatedafter the second data block and stored in the temporary storage circuit3.

When the RS code is used as the second error-correcting code, the seconddata block has a size corresponding to write data (4096bits)×8+error-detecting code (32 bits)×8 and corrects a 12-bit error inthe second data block. To correct an error having such a size in thesecond data block, the second error-correcting code Dd has a size of,e.g., 192 bits. Those skilled in the art already know the detailedarrangement of the second error-correcting code generation unit 8, and adescription thereof will be omitted.

The second error-correcting code Dd is concatenated after the seconddata block in the above-described processes, thereby obtaining atransfer data block (the structure in the temporary storage circuit 3 inFIG. 5). The transfer data block is supplied to the semiconductor memory2. The semiconductor memory 2 stores each transfer data block.

[Arrangement of Read System Circuit]

FIG. 6 is a block diagram illustrating the main portion of the errorcorrection circuit 1 associated with data read.

As shown in FIG. 6, the semiconductor memory 2 supplies a signal S1 to afirst error correction unit 11. The signal S1 is formed from a transferdata block (the structure in the temporary storage circuit 3 in FIG. 5).

If the first data blocks D1 to D8 contain errors, the first errorcorrection unit 11 corrects the errors in the first data blocks D1 to D8using the first error-correcting codes Dc1 to Dc8 in the signal S1,respectively, within the bounds of the capability of the first errorcorrection unit 11. More specifically, the first error correction unit11 corrects the errors in the first data block D1 using the firsterror-correcting code Dc1. Similarly, the first error correction unit 11corrects the errors in the first data blocks D2 to D8 using theerror-correcting codes Dc2 to Dc8, respectively, within the bounds ofthe capability of the first error correction unit 11.

The first error correction unit 11 outputs a signal S2 obtained bycorrecting the errors in the signal S1 using the first error-correctingcodes. If the number of error bits in the first data blocks D1 to D8before error correction is equal to or less than the error correctioncapability of the first error correction unit 11, the first data blocksD1 to D8 in the signal S2 after error correction contain no errors.However, if the number of error bits in the first data blocks D1 to D8before error correction exceeds the error correction capability of thefirst error correction unit 11, the first data blocks D1 to D8 in thesignal S2 after error correction still contain errors.

The signal S2 is supplied to an error detection unit 12 and a seconderror correction unit 13. The error detection unit 12 detects errors inthe write data items Da1 to Da8 using the error-detecting codes Db1 toDb8. The error detection unit 12 directly supplies the signal S2 to aselection unit 14. The error detection unit 12 also supplies, to theselection unit 14, a signal S3 representing the presence/absence oferror detection in all the first data blocks D1 to D8. The errordetection unit 12 supplies, to the second error correction unit 13, asignal S4 containing information representing error detection locationsin the first data blocks D1 to D8 in addition to the presence/absence oferror detection.

The second error correction unit 13 analyzes the signal S4 and acquiresinformation representing whether errors are detected upon errordetection by the error detection unit 12. If no errors are detected,error correction is not necessary any more. For example, the seconderror correction unit 13 stops the operation for the signal S2 of theprocess target as power supply from a power supply circuit (not shown)or clock signal supply from a clock circuit (not shown) stops.

Upon analyzing the signal S4 and acquiring information representing thaterrors are detected in the signal S2, the second error correction unit13 corrects the errors in the first data blocks D1 to D8 using thesecond error-correcting code Dd. At this time, the second errorcorrection unit 13 executes error correction for only the first datablocks D1 to D8 containing errors. FIG. 7 shows an example of thisstate.

FIG. 7 shows an example in which errors are detected in the first datablocks D2, D4, and D5. The second error correction unit 13 executessyndrome calculation using the second error-correcting code Dd for allthe first data blocks D1 to D8. On the other hand, the second errorcorrection unit 13 executes Chien search for only the first data blocksD2, D4, and D5 containing the detected errors. The second errorcorrection unit 13 corrects the errors in the first data blocks D2, D4,and D5 using the second error-correcting code Dd. The second errorcorrection unit 13 outputs a signal S5 obtained by correcting the errorsin the signal S2 using the second error-correcting code.

Error correction by the second error correction unit 13 is sequentiallyexecuted for the errors detected in the first data blocks D1 to D8,unlike the prior art. That is, no error correction circuit dedicated toeach of the first data blocks D1 to D8 is provided. This reduces thecircuit scale and power consumption of the second error correction unit13.

Depending on the number of first data blocks to be subjected to errorcorrection, the necessary time may be longer than in parallel errorcorrection by the dedicated circuits of the first data blocks D1 to D8.In this embodiment, however, the second error correction unit 13executes Chien search for only, of the first data blocks D1 to D8, datablocks containing detected errors. In addition, the firsterror-correcting code is designed to be able to correct most (nearly100%) of the errors in the first data blocks D1 to D8 by only correctionusing the first error-correcting code. For this reason, the seconderror-correcting code is rarely used. In this embodiment, it istherefore possible to reduce the circuit scale and power consumption ofthe second error correction unit 13 without any increase in theprocessing time by sharing the error correction circuit for the firstdata blocks D1 to D8.

Assume that in a process of repeatedly reading certain a transfer datablock from the memory device, the error detection unit 12 detects noerror in the transfer data block which is read for the first time. Inthis case, at least one of power supply and clock signal supply to thesecond error correction unit 13 is stopped in advance in reading thetransfer data block for the second and subsequent times. This largelyreduces the power consumption in the error correction circuit 1 inreading the same transfer data block.

How to decide the correction capability of the first error correctionunit 11 and that of the error detection unit 12 will be described next.Note that the correction capability of the first error correction unit11 also includes the process of causing the first error-correcting codegeneration units 61 to 68 to generate the first error-correcting codesDc1 to Dc8. Similarly, the correction capability of the second errorcorrection unit 13 also includes the process of causing the seconderror-correcting code generation unit 8 to generate the seconderror-correcting code Dd.

FIG. 8 is a graph illustrating the relationship between the necessarycorrection capability and the elapsed time from data write in thesemiconductor memory 2. As shown in FIG. 8, as the elapsed time becomeslong, the number of errors in the data written in the semiconductormemory 2 increases. The error correction capability is changed inaccordance with the increase in the number of errors. The errorcorrection capability of the first error correction unit 11 and that ofthe second error correction unit 13 are decided so that an excessive orinsufficient error correction capability are used. More specifically,the error correction capability of the first error correction unit 11and that of the second error correction unit 13 are decided such thaterror correction can be done solely by the first error correction unit11 when the elapsed time is short, while the first error correction unit11 and the second error correction unit 13 can execute error correctionwhen the elapsed time exceeds a predetermined time (the time when thenumber of errors abruptly increases).

FIG. 9 shows the concept of the process range of the first errorcorrection unit 11 and that of the second error correction unit 13according to this embodiment. The abscissa in FIG. 9 represents thenumber of errors within a predetermined range (a page of a NAND flashmemory) of the semiconductor memory 2. The ordinate represents the erroroccurrence probability. The broken line indicates the relationshipbefore degradation of the semiconductor memory 2 (immediately afterwrite). The solid line indicates the relationship after degradation ofthe semiconductor memory 2 (after the guaranteed data retention time haselapsed).

As shown in FIG. 9, the error correction capability of the first errorcorrection unit 11 is decided such that only the first error correctionunit 11 can correct all errors when the number of errors within thepredetermined range is small. More specifically, the number ofcorrectable bits, error correction method, and the number of bits of anerror-correcting code are decided. For example, the error correctioncapability of the first error correction unit 11 is decided such that itcan correct almost 100% of errors before degradation and about 99% oferrors after degradation. On the other hand, the error correctioncapability of the second error correction unit 13 is decided to correctthe remaining 1% of errors after degradation.

As a result, the use probability of the second error correction unit 13rises along with the increase in the error rate, as shown in FIG. 10.

As described above, the first error correction unit 11, which has alower error correction capability but requires a shorter processing timeand lower power consumption, corrects almost all errors. The seconderror correction unit 13, which requires a longer processing time andhigher power consumption but has a higher error correction capability,corrects the remaining errors. The error correction circuit 1 cantherefore achieve a short processing time, low power consumption, andsmall circuit scale while maintaining a high error correctioncapability.

FIG. 11 shows the relationship between the error rate and the averagedChien search range of the second error correction unit 13. In thisembodiment (solid line), the error correction capability of the firsterror correction unit 11 is set such that most errors can be correctedby only the first error correction unit 11, as described above. For thisreason, even when the error rate is high, the second error correctionunit 13 is rarely involved in error correction, as compared to the priorart (broken line).

As described above, according to the semiconductor memory device of theembodiment, the plurality of first data blocks D1 to D8 each containinga corresponding one of a plurality of write data items are formed. Theplurality of first error-correcting codes Dc1 to Dc8 are generated forthe plurality of first data blocks D1 to D8, respectively. Additionally,the second error-correcting code Dd is generated for a second data blockformed from the plurality of first data blocks D1 to D8. When the numberof error bits is small, correction is done using the firsterror-correcting codes Dc1 to Dc8 which have a low capability butrequire low power consumption and a small circuit scale. When the numberof error bits is large, correction is done using both the firsterror-correcting codes Dc1 to Dc8 and the second error-correcting codeDd which requires high power consumption and a large circuit scale butallows correction with a high capability. Hence, there is provided asemiconductor memory device whose error correction circuit 1 has anappropriate circuit scale and power consumption and shortens the errorcorrection time without sacrificing the error correction capability.

In this embodiment, error correction using the second error-correctingcode Dd is executed for, of the first data blocks D1 to D8, only datacontaining errors even after error correction using the firsterror-correcting codes Dc1 to Dc8. This can greatly reduce the circuitscale of the second error correction unit 13 as compared to an examplein which circuits for executing error correction using the seconderror-correcting code Dd are provided in correspondence with theplurality of first data blocks D1 to D8.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. (canceled)
 2. A storage device comprising: a nonvolatilesemiconductor memory configured to store a plurality of detecting codesto respectively detect an error in a plurality of data items, aplurality of first correcting codes to respectively correct an error ina plurality of first data blocks each of which comprises one of the dataitems and a corresponding detecting code, a second correcting code tocorrect an error in a second data block which comprises the first datablocks, and the second data block; a first corrector configured tocorrect an error in the first data blocks using the first correctingcodes, respectively; a detector configured to detect an error in thedata items corrected by the first corrector using the detecting codes,respectively; and a second corrector configured to correct an error in adata item containing the error of the corrected data items using thesecond correcting code.
 3. The device according to claim 2, wherein anerror correction capability of the second correcting code is higher thanerror correction capabilities of the first correcting codes.
 4. Thedevice according to claim 2, wherein the second corrector stops acorrection process when the data items corrected by the first correctorcontain no error.
 5. The device according to claim 2, wherein thedetector generates error information representing presence/absence of anerror in each of the corrected data items.
 6. The device according toclaim 2, wherein the semiconductor memory is a NAND flash memory.
 7. Astorage device comprising: a nonvolatile semiconductor memory configuredto store a plurality of detecting codes to respectively detect an errorin a plurality of data items, a plurality of first correcting codes torespectively correct an error in a plurality of first data blocks eachof which comprises one of the data items and a corresponding detectingcode, a second correcting code to correct an error in a second datablock which comprises the first data blocks, and the second data block;a first corrector receiving the first data blocks and configured tocorrect an error in the first data blocks using the first correctingcodes, respectively; a detector receiving the data items corrected bythe first corrector and configured to detect an error in the correcteddata items using the detecting codes, respectively; and a secondcorrector receiving the second data block corrected by the firstcorrector and configured to correct an error in the corrected seconddata block using the second correcting code, based on a detection resultby the detector.
 8. The device according to claim 7, wherein an errorcorrection capability of the second correcting code is higher than errorcorrection capabilities of the first correcting codes.
 9. The deviceaccording to claim 7, wherein the second corrector stops a correctionprocess when the data items corrected by the first corrector contain noerror.
 10. The device according to claim 7, wherein the detectorgenerates error information representing presence/absence of an error ineach of the corrected data items.
 11. The device according to claim 7,wherein the semiconductor memory is a NAND flash memory.
 12. A storagedevice comprising: a nonvolatile semiconductor memory configured tostore first data; a first corrector configured to correct first errordata in the first data using first correcting code data; a detectorconfigured to detect second error data which has not been corrected bythe first corrector, using detecting code data; and a second correctorconfigured to correct the second error data using second correcting codedata.
 13. A storage device comprising: a nonvolatile semiconductormemory configured to store data; and a processor for controlling thenonvolatile memory configured to correct data by using first errorcorrecting codes, wherein the processor monitors error bit levels atread operations to prevent data corruption caused by a number ofaccumulated error bits exceeding a correcting capability of the firsterror correcting codes, and when the number of error bits reaches athreshold, the processor restores the data to its original, error-freestate without using the first error correcting codes.
 14. The deviceaccording to claim 13, wherein the processor uses a BCH ECC algorithmper data unit which is an integral multiple of 512 bytes.
 15. The deviceaccording to claim 13, wherein the data is written into the nonvolatilesemiconductor memory by page unit.
 16. The device according to claim 15,wherein the data is erased from the nonvolatile semiconductor memory byblock unit, and the block comprises pages.
 17. The device according toclaim 13, wherein the processor uses a CRC (cyclic redundancy checksum)as an error detecting code.
 18. The device according to claim 13,further comprising: an interface; a first circuit coupled to theinterface; a second circuit for interfacing with the memory; and a thirdcircuit coupled to the second circuit, wherein the first circuit isconfigured to: generate first error detection data for data receivedfrom the interface; and check data transmitted to the interface, whereinthe third circuit is configured to check data and error correction datareceived from the second circuit.
 19. The device according to claim 18,wherein the first circuit is configured to generate error detection dataper received unit of data.
 20. The device according to claim 19, whereinthe data received from the interface comprises a data payload includinga number of units of data, and the data received from the interfacecomprises streaming data.
 21. The device according to claim 18, whereinthe first circuit comprises a cyclic redundancy check (CRC) enginecoupled to the interface, and the third circuit comprises an errorcorrection code (ECC) engine.
 22. The device according to claim 18,wherein the processor includes: a fourth circuit coupled to theinterface and to the second and third circuits; and an error detectionmemory coupled to the fourth circuit, wherein the error detection memoryis configured to store the error detection data.
 23. The deviceaccording to claim 22, wherein the processor includes a data buffercoupled to the fourth circuit and to the third circuit, wherein the databuffer is configured to buffer data for the third circuit.
 24. Thedevice according to claim 18, wherein the third circuit is configured tocorrect one or more errors in the data received from the second circuit.25. The device according to claim 18, wherein the processor isconfigured to transfer the data received from the interface, the errordetection data, and the error correction data across the second circuit.26. The device according to claim 18, wherein the processor includes: afourth circuit coupled to the interface and to the second and thirdcircuits, wherein the fourth circuit is configured to receive data andcorresponding error detection data from the second circuit and totransfer the data and the corresponding error detection data to thefirst circuit.
 27. The device according to claim 26, wherein the firstcircuit is configured to: generate error detection data for the datareceived from the fourth circuit; and compare the generated errordetection data for the data received from the fourth circuit tocorresponding error detection data received from the fourth circuit. 28.The device according to claim 26, wherein the processor includes: morethan one channel; a channel data transfer circuit coupled to the fourthcircuit; a data buffer coupled to the channel data transfer circuit andthe third circuit; and an error detection circuit coupled to the secondcircuit.
 29. A storage device comprising: a nonvolatile semiconductormemory configured to store data; and a processor for controlling thenonvolatile memory configured to correct data by using first errorcorrecting codes, wherein the processor refers to error bit levels at aread operation, and when a number of error bits accumulated in the readtransaction exceeds a correcting capability of the first errorcorrecting codes, the processor processes the data to its original,error-free state using a method except for an algorithm using the firsterror correcting code.
 30. The device according to claim 29, wherein theprocessor uses a BCH ECC algorithm per data unit which is an integralmultiple of 512 bytes.
 31. The device according to claim 29, wherein thedata is written into the nonvolatile semiconductor memory by page unit.32. The device according to claim 31, wherein the data is erased fromthe nonvolatile semiconductor memory by block unit, and the blockcomprises pages.
 33. The device according to claim 29, wherein theprocessor uses a CRC (cyclic redundancy checksum) as an error detectingcode.
 34. The device according to claim 29, further comprising: aninterface; a first circuit coupled to the interface; a second circuitfor interfacing with the memory; and a third circuit coupled to thesecond circuit, wherein the first circuit is configured to: generatefirst error detection data for data received from the interface; andcheck data transmitted to the interface, wherein the third circuit isconfigured to check data and error correction data received from thesecond circuit.
 35. The device according to claim 34, wherein the firstcircuit is configured to generate error detection data per received unitof data.
 36. The device according to claim 35, wherein the data receivedfrom the interface comprises a data payload including a number of unitsof data, and the data received from the interface comprises streamingdata.
 37. The device according to claim 34, wherein the first circuitcomprises a cyclic redundancy check (CRC) engine coupled to theinterface, and the third circuit comprises an error correction code(ECC) engine.
 38. The device according to claim 34, wherein theprocessor includes: a fourth circuit coupled to the interface and to thesecond and third circuits; and an error detection memory coupled to thefourth circuit, wherein the error detection memory is configured tostore the error detection data.
 39. The device according to claim 38,wherein the processor includes a data buffer coupled to the fourthcircuit and to the third circuit, wherein the data buffer is configuredto buffer data for the third circuit.
 40. The device according to claim34, wherein the third circuit is configured to correct one or moreerrors in the data received from the second circuit.
 41. The deviceaccording to claim 34, wherein the processor is configured to transferthe data received from the interface, the error detection data, and theerror correction data across the second circuit.
 42. The deviceaccording to claim 34, wherein the processor includes: a fourth circuitcoupled to the interface and to the second and third circuits, whereinthe fourth circuit is configured to receive data and corresponding errordetection data from the second circuit and to transfer the data and thecorresponding error detection data to the first circuit.
 43. The deviceaccording to claim 42, wherein the first circuit is configured to:generate error detection data for the data received from the fourthcircuit; and compare the generated error detection data for the datareceived from the fourth circuit to corresponding error detection datareceived from the fourth circuit.
 44. The device according to claim 42,wherein the processor includes: more than one channel; a channel datatransfer circuit coupled to the fourth circuit; a data buffer coupled tothe channel data transfer circuit and the third circuit; and an errordetection circuit coupled to the second circuit.